A long-recognized important objective in the constant advancement of monolithic IC (Integrated Circuit) technology is the scaling-down of IC dimensions. Such scaling-down of IC dimensions reduces area capacitance and is critical to obtaining higher speed performance of integrated circuits. Moreover, reducing the area of an IC die leads to higher yield during IC fabrication. Such advantages are a driving force to constantly scale down IC dimensions.
With the scaling down of integrated circuit dimensions, openings, which are etched within the integrated circuit, are reduced in size. The aspect ratio of the opening, which is defined as the ratio of the width of the opening to the depth of the opening, increases with scaling down of integrated circuit dimensions.
Etch selectivity refers to how closely a desired etched area has been etched out during an etch process. The desired etched area is defined by a masking layer over the area to be etched. Depending on the etch process, the actual etched area may deviate from the desired etched area. An etch process having a high (i.e., good) etch selectivity results in an opening having an area that is substantially close to the desired etched area. An etch process having a low (i.e., poor) etch selectivity results in an opening having an area that substantially deviates from the desired etched area.
When etching openings with high aspect ratios, the etch selectivity becomes especially critical for controlling the location and shape of small-geometry integrated circuit dimensions. Thus, an etch process which is amenable for high etch selectivity is especially important for small-geometry integrated circuit fabrication.
The present invention is described with a dual damascene etch process for etching out a trench line and a via hole for integrated circuit metallization. However, as would be apparent to one of ordinary skill in the art, the present invention may be applied to etching any other type of openings within an integrated circuit.
As an integrated circuit is scaled down, metallization, which interconnects devices on the integrated circuit, is also scaled down. Metal lines for scaled-down integrated circuits are fabricated using a damascene etch process. In such a process, a trench line is etched within an insulating layer. That trench line is then filled with metal or any other conductive material. The surface of the integrated circuit is then polished to form conductive lines with the conductive material contained within the trench lines.
Referring to FIG. 1, integrated circuits typically include multi-level metallization. A first metal line 102 is contained within a first trench line 104 etched in a first trench insulating layer 106. A second metal line 108 is contained within a second trench line 110 etched in a second trench insulating layer 112. The first metal line 102 is on a first metallization level on the integrated circuit, and the second metal line 108 is on a second metallization level on the integrated circuit. A via interconnects the metal lines 102 and 108 on the two different metallization levels. A via plug 114 is comprised of a conductive material and is disposed within a via hole 116 etched in a via insulating layer 118. The insulating layers 106, 112, and 118 are comprised of any insulating material such as any form of oxides as is known to one of ordinary skill in the art.
Referring to FIG. 2, if the second trench line 110 and the via hole 116 were not filled with a conductive material, a top view of the integrated circuit of FIG. 1 shows the second trench line 110 running over the via hole 116. The first metal line 102 is disposed on the bottom of the via hole 116. FIG. 1 is a cross-sectional view of the integrated circuit of FIG. 2 along line AA after the via hole 116 and the second trench line 110 have been filled with a conductive material.
A dual damascene etch refers to an etching process whereby a via hole and a trench line are etched away with one etching step or a series of etching steps. Referring to FIG. 3A (which shows a cross-section along line AA of the integrated circuit of FIG. 2), a prior art dual damascene etch process includes a step of depositing a bottom nitride layer 302 adjacent a first metal layer 304. A via insulating layer 306 is deposited adjacent the bottom nitride layer 302.
A via masking layer 308 is deposited adjacent the via insulating layer 306. The via masking layer 308 is etched to have a via pattern for defining a via hole in the via insulating layer 306. The via masking layer typically is comprised of a hard mask material such as nitride or any other type of dielectric material which is known to one of ordinary skill in the art to be an etch-stop material.
A trench insulating layer 310 is deposited adjacent the via masking layer 308. Then, a photoresist layer 312 is deposited adjacent the trench insulating layer 310. The photoresist layer 312 is further processed to have a trench pattern for defining a trench line in the trench insulating layer 310. The via pattern in the via masking layer and the trench pattern in the photoresist layer are aligned such that a first conductive material filled within the via hole forms a conductive path with a second conductive material filled within the trench line, as illustrated in FIGS. 1 and 2.
Referring to FIG. 3B, a trench line 314 is etched out of the trench insulating layer 310 with the photoresist layer 312 defining the size, shape, and location of the trench line 314. Furthermore, in a dual damascene etch process, a via hole 316 is also etched out of the via insulating layer 306. Referring to FIG. 3A, the trench insulating layer 310 abuts the via insulating layer 306. Thus, using a dual damascene etch process, the trench line 314 and the via hole 316 are etched with one etching step, and the trench line 314 and the via hole 316 are contiguous openings.
Referring to FIG. 3C, any part of the masking layers 302 and 308 (and the nitride layer 302) that are exposed are etched away. Then, the via hole 316 and the trench line 314 are filled with conductive material. The conductive material in the via hole 316 forms a conductive path between the first metal layer 304 and the conductive material in the trench line 314.
With the prior art etch process of FIG. 3, because a photoresist layer 312 is used to define the trench line, a high temperature etch cannot be used since high temperatures lead to reflow of the photoresist layer 312. Thus, with the photoresist layer 312 being the top layer during the etch process, a temperature in the range of 0.degree. C. to 20.degree. C. is typically used in the prior art. However, as known to one of ordinary skill in the art of IC fabrication, an etch using a lower temperature is disadvantageous with lower etch selectivity.
Furthermore, with the use of the photoresist layer 312 being the top layer, a high polymer etch does not readily etch down to the bottom of the via hole 316. The photoresist layer 312 adds extra depth to the openings 314 and 316 to be etched. Furthermore, a high polymer etch tends to deposit polymer as a by-product of the etch These factors lead to deposit of polymer within the via hole 316 resulting in an etch-stop before the via hole 316 is completely etched out. However, as known to one of ordinary skill in the art of IC fabrication, a high polymer etch also results in high etch selectivity and would be desirable for small-geometry integrated circuit fabrication.
Thus, an etch process which allows etching openings in an integrated circuit using a high temperature etch and/or a high polymer etch would be desirable for high etch selectivity. Such high etch selectivity is especially advantageous for small-geometry integrated circuit fabrication.